The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. An MOS transistor includes a gate electrode as a control electrode and spaced apart source and drain regions between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel between the source and drain regions.
The gain of an MOS transistor, usually defined by the transconductance (gm), is proportional to the mobility (μ) of the majority carrier in the transistor channel. The current carrying capability and hence the performance of an MOS transistor is proportional to the mobility of the majority carrier in the channel. The mobility of holes, the majority carrier in a P-channel MOS (PMOS) transistor, and the mobility of electrons, the majority carrier in an N-channel MOS (NMOS) transistor, can be enhanced by applying an appropriate stress to the channel. The known stress engineering methods greatly enhance circuit performance by increasing device drive current without increasing device size and device capacitance. It is known, for example, that a tensile stress liner applied to an NMOS transistor induces a longitudinal stress in the channel and enhances the majority carrier electron mobility, but a tensile stress liner applied to a PMOS transistor results in a decrease in majority carrier hole mobility. Similarly, a compressive stress liner applied to a PMOS transistor induces a compressive stress in the channel and enhances the hole mobility, but if applied to an NMOS transistor the compressive stress liner decreases majority carrier electron mobility. As ICs become larger and larger, the size of individual transistors shrinks and the spacing between NMOS and PMOS transistors also shrinks. As the spacing between NMOS and PMOS transistors becomes smaller, the interaction between tensile and compressive liners becomes more and more important. The interaction between different stress liners can adversely affect the mobility enhancement potentially available from use of the liners.
Accordingly, it is desirable to provide optimized methods for fabricating high density CMOS circuits using dual stress liners to enhance mobility in both NMOS and PMOS transistors. In addition, it is desirable to provide stress enhanced CMOS circuits fabricated with dual stress liners. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.